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Texas Instruments /CC13x0 /PRCM /UARTCLKGDS

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Interpret as UARTCLKGDS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_EN)CLK_EN

Description

UART Clock Gate For Deep Sleep Mode

Fields

CLK_EN

CLK_EN

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data